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tenths of a volt less than Vp, so Vp must have the proper amplitude to fully drive the VCO s DC control input) After completing the filter s design calculations for the frequency synthesizer, the following final PLL design checks must be performed to confirm that the PLL will function as desired: 1 The loop bandwidth fc should be at least 1/20 FCOM 2 Make sure that C3 is at least 5 times larger in value than the input capacitance of the VCO (which is usually around 20 pF for the average VCO input capacitance) 3 Since maximum PLL phase detector input frequencies normally are no higher than 10 MHz, make sure that FCOM is not above this amount 4 R must generally be set to divide by at least 3 or more 5 Check the completed PLL design to confirm that the damping factor is less than 1 by: R2C2 2 6 Check that R3/R2 2 K KVCO N (C1 C2 C3)

Figure 5-21: Router 1 and router 2 configuration from Figure 5-20

7 The optimization index can be checked by: T2 1 ( CT2)2 T1 T3 1 ( CT1)2 1 ( CT3)2

This formula confirms that the loop is stable with a fast lock time Any value between 90 and 100 percent is considered stable

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To start, click the Brush tool icon in the Toolbox, position the cursor over your canvas, then click and drag You should notice that the Brush paints with the color that s specified as the foreground color (at the bottom of the Toolbox) The Brush worked as expected, but there s a lot more to consider than just color Any time you choose a tool from the Toolbox, you should make a pit stop at the Options bar before putting the tool to work In the case of the Brush tool, it s where you can pick a brush size, a shape, and control how it behaves The brush can be a big soft watercolor brush or a hard-edged, fine-tipped brush It can even act like an airbrush or use different strengths of paint We ll show you some important Options bar settings as we proceed, but for now, we just want to show how to find the various brushes at your disposal

Data Link Switching Now let's look at the DLSw standard, as defined in RFC 1745 DLSw was designed to allow the transportation of SNA and NetBIOS traffic over an IP wide area network The standard came into being largely as a result of problems encountered when trying to scale source route bridging to larger networks Problems inherent in the source route bridge protocol include: Bridge hop-count limit of 7 Excessive generation of broadcast explorer packets, consuming WAN bandwidth Unwanted timeouts at the Data Link level over WAN links

Downloaded from Digital Engineering Library @ McGraw-Hill (wwwdigitalengineeringlibrarycom) Copyright 2004 The McGraw-Hill Companies All rights reserved Any use is subject to the Terms of Use as given at the website

lock time, s higher frequency, Hz lower frequency, Hz frequency tolerance (or acceptable frequency error at lock), Hz

You have the Brush tool in hand, so now you need to decide how big or round or soft you want the tip to be Click the brush sample in the Options bar (see Figure 6-5) to see the choices in the Brushes pop-up palette

It is important to realize that DLSw is not a layer 3 protocol and therefore does not perform routing DLSw is a layer 2 protocol and works on the basis of establishing a DLSw circuit between two routers in an IP network When DLSw is implemented, local Data Link level (layer 2) communications are terminated at the local router, enabling that router to provide link-level acknowledgments This functionality effectively turns a connection between two machines communicating via a DLSw router pair into three sections At each end of the link, the machines will establish a connection with the DLSw router (typically a source route connection), and the two DLSw routers will establish TCP connections to carry the traffic over the IP WAN In Fig 5-22, PC A exchanges link-level acknowledgments with router 1, and PC B exchanges link-level acknowledgments with router 2; router 1 and router 2 exchange DLSw information via TCP connections

9 To check for approximate phase noise (PN) of the PLL at 150 Hz from the center frequency: PN @ 150 Hz 205 10 log FCOM 20 log (N counter value), where 205 is the average value for a typical PLL chip, and is referred to as the PLL s 1 Hz normalized PN floor, or 1 Hz PNF This formula does not take into account a noisy VCO

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